The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to a specific logic operations. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
A typical design cycle for determining the configuration of a programmable device, referred to compilation, starts with an extraction phase, followed by a logic synthesis phase, a fitting phase, and an assembly phase. The extraction phase takes a user design, typically expressed as a netlist in a hardware description language such as Verilog or VHDL, and produces a set of logic gates implementing the user design. In the logic synthesis phase, the set of logic gates is permutated over the hardware architecture of the programmable device in order to match elements of the user design with corresponding portions of the programmable device. The fitting phase assigns the various portions of the user design to specific logic cells and functional blocks and determines the configuration of the configurable switching circuit used to route signals between these logic cells and functional blocks, taking care to satisfy the user timing constraints as much as possible. In the assembly phase, a configuration file defining the programmable device configuration is created. The configuration can then be loaded into a programmable device to implement the user design.
To satisfy the requirements of a user design, one or more additional optimization phases can be used to optimize the user design. Optimization phases can optimize a user design with respect to a number of different criteria, including as overall execution speed, programmable device resource consumption (referred to as area), and power consumption. To yield greater performance of the user design as implemented by the programmable device, it is often desirable to process the user design with two or more optimization phases.
However, this approach often leads to difficulties. For example, a first optimization phase may optimize a user design so thoroughly that a second optimization phase does not have sufficient “room” to effectively further optimize the user design. Conversely, a second optimization phase, in the course of attempting to optimize the user design, may undo the optimizations added by a previously executed optimization phase. Additionally, running multiple optimization phases can greatly increase the amount of time required to compile the user design.
As user designs are developed, designers typically invest substantial time and resources to optimize the user design to satisfy a set of design requirements. Designers often need to make small changes to the user design to correct mistakes or satisfy additional requirements. To implement these changes, referred to change orders, the modified user design must be re-compiled. During compilation, the small change in the user design will often cascade into a drastically different compiler output. As a result, the designers often lose many of the optimizations previously to the original user design and must begin anew to re-optimize the modified user design.
It is therefore desirable for a system and method to improve the efficacy of combinations of optimization phases to improve the performance of user designs. It is further desirable to decrease the compilation time required to optimize user designs with combinations of optimization phases. It is also desirable that the optimization of modified versions of a user design does not unnecessarily discard previous optimizations.